The RAMDAC address space is complex in that it is shared by the RAMDAC and LeoCross. Furthermore, access to the RAMDAC and LeoCross internal state is of two types, direct and indirect.
The indirect type of access requires two SBus transactions. In the first transaction, the software writes an index value into the RAMDAC Address Pointer register, which points to the register or memory that is to be accessed in a following transaction. In the second transaction, the actual register or memory identified in the address map by that index is accessed. The RAMDAC automatically increments the address pointer to accommodate access to contiguous memory locations in the Color Table.
The RAMDAC Address Map is shown in Table 8-1 for State Set 0. Note that the mapping occurs twice, once for State Set 0 and once for State Set 1. To access State Set 1, add 0x100 000 to the SBus address shown for State Set 0. In this table, the locations are listed in order by SBus address and then by index value. However, the registers are described in this chapter in a functional order. The page column in the Address Map refers to the page where that register is described.
Table 8-1 RAMDAC Address Map - State Set 0
----------------------------------------------------------
Page SBus Index Access Register Address ----------------------------------------------------------
8-2 0x060 0020 Direct R/W RAMDAC Address Pointer 8-7 0x060 0024 0x00 R/W Color Table, Word 0 Ø Ø 0xFF Color Table, Word 255 8-10 0x060 0028 0x00 Read Pixel Test 8-10 0x060 0028 0x01 R/W DAC Test 8-11 0x060 0028 0x02 R/W Sync, Blank, & IPLL Test 8-9 0x060 0028 0x03 Read ID 8-9 0x060 0028 0x04 R/W Pixel Mask 8-5 0x060 0028 0x06 R/W Command Register 2 8-6 0x060 0028 0x07 R/W Command Register 3 8-3 0x060 002C Direct R/W RAMDAC Mode ----------------------------------------------------------
This section describes the data formats of the registers in the RAMDAC Register Address Space.
0x060 0020 for State Set 0
0x160 0020 for State Set 1
State Set 0 and 1; Read and Write
This is the RAMDAC address pointer used to point to the indirectly accessed memory and registers.
0x060 002C for State Set 0
0x160 002C for State Set 1
State Set 0 and 1; Read and Write
The RAMDAC Mode register controls various RAMDAC operations as described in the "Bit Fields" section.
D<7:6 = Palette Select Control
Allows up to four palette devices (color tables) to work together. Each palette
device contains 256 30-bit words. Only one palette device may be selected at
any particular instant. The control signals for these bits are multiplexed,
allowing for sub-pixel resolution. This allows up to four windows to be
controlled by separate palettes. For Leo, these bits are normally set to 00.
D<4:3 = Operational Mode Control
These bits allow debugging of the RAMDAC and its interface to other devices.
Test registers monitor the pixel port, RAM, and the DAC port. The RAMDAC
Mode register and Control Register 2 control the test modes. Data is latched in
the test registers along the video path by either the pixel clock or by using bit 7
of the Red pixel data as a trigger bit. The pixel data trigger is useful when the
pixel clock is connected to a free running source.
D<2 = CXBus Data Width
Specifies the data bus width of the CXBus.
D<1 = Resolution Control
Specifies the resolution control.
D<0 = Reset Control
Resets the pixel port sampling sequence to ensure that the pixel sequence AB
starts at A. To reset the sampling sequence, write a 1, then a 0, and then a 1 to
this bit.
0x060 0028, index 0x06, State Set 0
0x160 0028, index 0x06, State Set 1
State Set 0 and 1; Read and Write
This is a 10-bit register that contains the control bits described under "Bit Fields" below. Only 8 bits are used.
D<7:4 = True Color & Pseudo Color Mode Control
Specify the color mode. The three 8-bit Pseudo Color modes allow the pixel
input data to be encoded on the red, green, or blue input pixel stream.
D<3 = Pedestal Enable Control
Specifies whether a 0 IRE or a 7.5 IRE blanking pedestal is generated on the
video outputs.
D<2 = Sync Recognition Control
Specifies whether the video sync input is encoded onto the analog video
current outputs or ignored.
D<1 = IPLL Trigger Control
Specifies whether the IPLL output is triggered from blank or sync.
D<0 = R7 Trigger Polarity Control
Determines whether the pixel data is latched into the test registers on the rising
or falling edge of red bit 7 (R7).
0x060 0028, index 0x07, State Set 0
0x160 0028, index 0x07, State Set 1
State Set 0 and 1; Read and Write
This is a 10-bit register that contains the control bits described under "Bit Fields" below. Only 8 bits are used.
D<7:6 = Pixel Multiplexer Control
Specify the RAMDACs multiplex mode. It thus also determines the frequency
of the loadout signal. Loadout is a divided down version of the pixel clock.
D<5:2 = Extra Blank Pipeline Delay Control
Specify the additional pipeline delay that can be added to the blank function,
relative to the overall RAMDAC pipeline delay. As the blank control normally
enters the Video DAC from a shorter pipeline than the video pixel data, this
control is useful in de-skewing the pipeline differential.
D<1:0 = Prgckout Frequency Control
Specify the output frequency of the Prgckout output from the RAMDAC.
Prgckout is a divided down version of the pixel clock.
0x060 0028, index = 0x00 thru 0xFF (256 words), State Set 0
0x160 0028, index = 0x00 thru 0xFF (256 words), State Set 1
State Set 0 and 1; Read and Write
The RAMDAC Color Table contains 256 30-bit words. It is normally thought of as three 256 word by 10-bit color lookup tables for the red, green and blue outputs.
The color palette may be programmed to be 24-bits deep (eight bits for red, green, and blue) instead of 30 (ten bits each). When configured as 24 bits deep, the least-significant bits of the ten-bit digital-to-analog converters are pulled down to zero, allowing for 256 output levels instead of 1024.
Access to the color table requires several operations. The first operation is a write to load the "RAMDAC Address Pointer" register with address of the starting word in the color table. The remaining operations depend whether the resolution control (see "RAMDAC Mode" register on page 8-3) is set for 8-bit or 10-bit mode.
When writing to or reading from the color table on a sequential basis, only the starting address needs to be specified. After a red, green, and blue access sequence, the address increments automatically.
For 8-bit mode, the second through fourth accesses of the color table are for the red, green, and blue tables, respectively. After the fourth access, the address increments automatically.
For 10-bit mode, six accesses of the color table are required before the address increments automatically. These accesses proceed in the following order:
Access the eight most-significant bits of the red color table.
Access the two least-significant bits of the red color table. These two bit values correspond to data bits 1 and 0 of the SBus.
Access the eight most-significant bits of the green color table.
Access the two least-significant bits of the green color table. These two bit values correspond to data bits 1 and 0 of the SBus.
Access the eight most-significant bits of the blue color table.
Access the two least-significant bits of the blue color table. These two bit values correspond to data bits 1 and 0 of the SBus.
The RAMDAC Color Table is used to provide gamma correction. Gamma correction solves two problems. First, it converts the linear coded color values stored in the LeoCross CLUTs to ratio values for display on the monitor. The ratio values are used because the eye is sensitive to ratios of intensity levels rather than their absolute values. Second, gamma correction compensates for any non-linearity in the monitor.
0x060 0028, index 0x04, State Set 0
0x160 0028, index 0x04, State Set 1
State Set 0 and 1; Read and Write
The contents of this register are individually bit-wise logically ANDed with the red, green, and blue pixel input streams of data.
0x060 0028, index 0x03, State Set 0
0x160 0028, index 0x03, State Set 1
State Set 0 and 1; Read only
Returns the value 0x8C, which identifies the RAMDAC as an Analog Devices ADV7152.
0x060 0028, index 0x00, State Set 0
0x160 0028, index 0x00, State Set 1
State Set 0 and 1; Read only
Allows diagnostic access to the pixel port. The test modes are controlled by the "RAMDAC Mode" register and "Command Register 2." See D<4:3 of the "RAMDAC Mode" register on page 8-3 for details.
0x060 0028, index 0x01, State Set 0
0x160 0028, index 0x01, State Set 1
State Set 0 and 1; Read and Write
Allows diagnostic access to the DAC port. The test modes are controlled by the "RAMDAC Mode" register and "Command Register 2." See D<4:3 of the "RAMDAC Mode" register on page 8-3 for details.
0x060 0028, index 0x02, State Set 0
0x160 0028, index 0x02, State Set 1
State Set 0 and 1; Read and Write
Allows diagnostic access to the three least significant bits of the sync, blank and IPLL pixel control bits. The test modes are controlled by the "RAMDAC Mode" register and "Command Register 2." See D<4:3 of the "RAMDAC Mode" register page 8-3 for details.
Note that IPLL is the phase locked loop output current that allows multiple RAMDACs to be synchronized with pixel resolution. This feature is not used for Leo.