The LeoCross address format is shown below.
A<24 = State Set
Set to 0 to select State Set 0. Set to 1 to select State Set 1. LeoCross registers are
available in both states.
A<13:12 = Page
Specifies the 4,096-byte page. Note that the Video Frame Counter is in page 2,
the cursor registers are in page 1, and the other registers are in page 0.
A<5:2 = Register Address
Coded as follows:
The LeoCross address space is complex in that it is shared by the RAMDAC and LeoCross. Furthermore, access to the RAMDAC and LeoCross internal state is of two types, direct and indirect. The direct type of state is accessed in a single SBus transaction.
The indirect type of access requires two SBus transactions. In the first transaction, the software writes the address pointer of the RAMDAC, cursor, or LeoCross, which points to the register or memory that is to be accessed in a following transaction. In the second transaction, the actual register or memory is accessed by accessing the indirect location shown in the address map. The address pointer is automatically incremented by circuits in the RAMDAC and LeoCross to accommodate access to contiguous memory and register locations.
The LeoCross Address Map is shown in Table 7-1 for State Set 0. Note that the mapping occurs twice, once for State Set 0 and once for State Set 1. To access State Set 1, add 0x100 000 to the SBus address shown for State Set 0. In this table, the locations are listed in order by SBus address and then by index value. However, the registers are described in this chapter in a functional order. The page column in the Address Map refers to the page where that register is described.
Table 7-1 LeoCross Address Map - State Set 0
--------------------------------------------------------------------------
Page SBus Index Access Register Address --------------------------------------------------------------------------
7-9 0x060 0000 Direct R/W LeoCross Address Pointer
7-21 0x060 0004 0x1000 R/W Image 0 CSR
7-21 0x060 0004 0x1001 R/W Image 1 CSR
7-21 0x060 0004 0x1002 R/W Image 2 CSR
7-22 0x060 0004 0x1003 R/W WID/FC CSR
7-25 0x060 0004 0x1005 R/W Interrupt Event
7-25 0x060 0004 0x1006 R/W Interrupt Enable Mask
7-26 0x060 0004 0x1007 Write Interrupt Clear Mask
7-48 0x060 0004 0x2000 Read LX Chip Code
7-49 0x060 0004 0x2001 Read Monitor ID
7-50 0x060 0004 0x2002 R/W DRAM Refresh Count
7-42 0x060 0004 0x2003 R/W Configuration Register Zero
7-44 0x060 0004 0x2004 R/W Configuration Register One
7-46 0x060 0004 0x2005 R/W Configuration Register Two
7-47 0x060 0004 0x2006 R/W Configuration Register Three
7-41 0x060 0004 0x2007 R/W Horizontal Counter Size
7-40 0x060 0004 0x2008 R/W HBlank End Address
7-40 0x060 0004 0x2009 R/W HBlank Start Address
7-38 0x060 0004 0x200A Read Horizontal Counter (Diagnostic Read)
7-39 0x060 0004 0x200B R/W HSynch End Address
7-39 0x060 0004 0x200C R/W HSynch Start Address
7-37 0x060 0004 0x200D R/W Vertical Counter Size
7-37 0x060 0004 0x200E R/W VBlank End Address
7-36 0x060 0004 0x200F R/W VBlank Start Address
7-36 0x060 0004 0x2010 R/W VSynch End Address
7-35 0x060 0004 0x2011 R/W VSynch Start Address
7-35 0x060 0004 0x2012 Read Vertical Counter (Diagnostic Read)
7-31 0x060 0004 0x2013 R/W Equalization Pulse End Address
7-31 0x060 0004 0x2014 R/W Equalization Pulse Start Address
7-32 0x060 0004 0x2015 R/W Equalization Interval 1 End Address
7-32 0x060 0004 0x2016 R/W Equalization Interval 1 Start Address
7-33 0x060 0004 0x2017 R/W Equalization Interval 2 End Address
7-33 0x060 0004 0x2018 R/W Equalization Interval 2 Start Address
7-34 0x060 0004 0x201A R/W Serration Pulse End Address
7-34 0x060 0004 0x201B R/W Serration Pulse Start Address
7-30 0x060 0004 0x201D R/W EXmach Loop Count
7-30 0x060 0004 0x201E R/W EXmach WID Start Address
7-29 0x060 0004 0x201F R/W EXmach Image Start Address
7-56 0x060 0004 0x2021 R/W Stereo Shutter Switch
7-57 0x060 0004 0x2022 Read CLUT Transfer Counter
7-56 0x060 0004 0x2023 Read WID Transfer Counter
7-50 0x060 0004 0x2024 Read DRAM Refresh Counter
7-51 0x060 0004 0x2027 R/W Video Clock Generator
7-15 0x060 0008 0x3000 R/W Image CLUT 0, Word 0, Bank 0
Ø
0x30FF
Image CLUT 0, Word 255, Bank 0
7-15 0x060 0008 0x3100 R/W Image CLUT 1, Word 0, Bank 0
Ø
0x31FF
Image CLUT 1, Word 255, Bank 0
7-15 0x060 0008 0x3200 R/W Image CLUT 2, Word 0, Bank 0
Ø
0x32FF
Image CLUT 2, Word 255, Bank 0
7-15 0x060 0008 0x3300 R/W Fast Clear Color 0, Bank 0
7-15 0x060 0008 0x3301 R/W Fast Clear Color 1, Bank 0
7-15 0x060 0008 0x3302 R/W Fast Clear Color 2, Bank 0
7-15 0x060 0008 0x3303 R/W Fast Clear Color 3, Bank 0
7-15 0x060 0008 0x3304 R/W Fast Clear Color 4, Bank 0
7-15 0x060 0008 0x3305 R/W Fast Clear Color 5, Bank 0
7-16 0x060 0008 0x3306 R/W Active Cursor Color 0, Bank 0
7-16 0x060 0008 0x3307 R/W Active Cursor Color 1, Bank 0
7-15 0x060 0008 0x3400 R/W Image CLUT-0, Word 0, Bank 1
Ø
0x34FF
Image CLUT-0, Word 255, Bank 1
7-15 0x060 0008 0x3500 R/W Image CLUT-1, Word 0, Bank 1
Ø
0x35FF
Image CLUT-1, Word 255, Bank 1
7-15 0x060 0008 0x3600 R/W Image CLUT-2, Word 0, Bank 1
Ø
0x36FF
Image CLUT-2, Word 255, Bank 1
7-15 0x060 0008 0x3700 R/W Fast Clear Color 0, Bank 1
7-15 0x060 0008 0x3701 R/W Fast Clear Color 1, Bank 1
7-15 0x060 0008 0x3702 R/W Fast Clear Color 2, Bank 1
7-15 0x060 0008 0x3703 R/W Fast Clear Color 3, Bank 1
7-15 0x060 0008 0x3704 R/W Fast Clear Color 4, Bank 1
7-15 0x060 0008 0x3705 R/W Fast Clear Color 5, Bank 1
7-16 0x060 0008 0x3706 R/W Active Cursor Color 0, Bank 1
7-16 0x060 0008 0x3707 R/W Active Cursor Color 1, Bank 1
7-15 0x060 0008 0x4000 R/W Shadow CLUT, Word 0
Ø Shadow CLUT, Word 255
0x40FF
7-15 0x060 0008 0x4100 R/W Shadow Fast Clear Color 0
7-15 0x060 0008 0x4101 R/W Shadow Fast Clear Color 1
7-15 0x060 0008 0x4102 R/W Shadow Fast Clear Color 2
7-15 0x060 0008 0x4103 R/W Shadow Fast Clear Color 3
7-15 0x060 0008 0x4104 R/W Shadow Fast Clear Color 4
7-15 0x060 0008 0x4105 R/W Shadow Fast Clear Color 5
7-18 0x060 0008 0x5000 R/W PWID LUT 0, Bank 0
Ø Ø
0x503F
PWID LUT 63, Bank 0
7-18 0x060 0008 0x5040 R/W QWID LUT 0, Bank 0
Ø Ø
0x504F
QWID LUT 15, Bank 0
7-18 0x060 0008 0x5100 R/W PWID LUT 0, Bank 1
Ø Ø
0x513F
PWID LUT 63, Bank 1
7-18 0x060 0008 0x5140 R/W QWID LUT 0, Bank 1
Ø Ø
0x514F
QWID LUT 15, Bank 1
7-18 0x060 0008 0x5200 R/W PWID LUT 0, Bank 2
Ø Ø
0x523F
PWID LUT 63, Bank 2
7-18 0x060 0008 0x5240 R/W QWID LUT 0, Bank 2
Ø Ø
0x524F
QWID LUT 15, Bank 2
7-18 0x060 0008 0x5300 R/W PWID LUT 0, Bank 3
Ø Ø
0x533F
PWID LUT 63, Bank 3
7-18 0x060 0008 0x5340 R/W QWID LUT 0, Bank 3
Ø Ø
0x534F
QWID LUT 15, Bank 3
7-18 0x060 0008 0x5400 R/W PWID LUT 0, Bank 4
Ø Ø
0x543F
PWID LUT 63, Bank 4
7-18 0x060 0008 0x5440 R/W QWID LUT 0, Bank 4
Ø Ø
0x544F
QWID LUT 15, Bank 4
7-18 0x060 0008 0x5800 R/W Shadow PWID LUT 0
Ø Ø
0x583F Shadow PWID LUT 63
7-18 0x060 0008 0x5840 R/W Shadow QWID LUT 0
Ø Ø
0x584F Shadow QWID LUT 15
7-9 0x060 0020 Direct R/W RAMDAC Address Pointer
8-7 0x060 0024 0x7000 R/W RAMDAC Color Table, Word 0
Ø Ø
0x70FF RAMDAC Color Table, Word 255
8-10 0x060 0028 0x7000 Read Pixel Test
8-10 0x060 0028 0x7001 R/W DAC Test
8-11 0x060 0028 0x7002 R/W Sync, Blank, & IPLL Test
8-9 0x060 0028 0x7003 Read ID
8-9 0x060 0028 0x7004 R/W Pixel Mask
8-5 0x060 0028 0x7006 R/W Command Register 2
8-5 0x060 0028 0x7007 R/W Command Register 3
8-3 0x060 002C Direct R/W RAMDAC Mode
7-10 0x060 1010 Direct R/W Cursor Address Pointer
7-23 0x060 1014 Direct R/W Cursor Control and Status Register
(CSR)
7-11 0x060 1018 Direct R/W Shadow Cursor Coordinate Address
7-13 0x060 101C 0x00 R/W Cursor Enable, Row 0
Ø Ø
Cursor Enable, Row 31
0x1F
7-13 0x060 101C 0x20 R/W Cursor Color, Row 0
Ø Ø
0x3F Cursor Color, Row 31
7-12 0x060 101C 0x40 Diag Active Cursor Coordinate Address
R/W
7-16 0x060 101C 0x50 R/W Shadow Cursor Color 0
7-16 0x060 101C 0x51 R/W Shadow Cursor Color 1
7-28 0x060 101C 0x80 Read Trap, Bank 0 (Even)
7-29 0x060 101C 0x81 Read Trap, Bank 1 (Odd)
7-51 0x060 200C Direct R/W Video Frame Counter
--------------------------------------------------------------------------
This section describes the data formats of the registers in the LeoCross Registers Address Space except for the RAMDAC registers. The data formats for the RAMDAC registers are described in Chapter 8, "RAMDAC Registers."
The registers are classified into the following groups:
"Address Pointers" on page 7-9
"Cursor Functions" on page 7-10
"Color Tables and Shadows" on page 7-14
"WID Look Up Table and Shadow" on page 7-17
"VINT OPS Control and Status Registers" on page 7-19
"Interrupt Registers" on page 7-24
"Trap Registers" on page 7-27
"EXmach Registers" on page 7-29
"Equalization Registers" on page 7-31
"Vertical Registers" on page 7-35
"Horizontal Registers" on page 7-38
"Configuration Registers" on page 7-41
"Other Registers" on page 7-48
A number of two-byte registers in the LeoCross chip have some high-order bit positions of an item to the right of low-order bit positions for that item when viewed on the SBus on shown in this manual.
For example, the "Stereo Shutter Switch" register looks like this on the SBus:
However, in the host data word, it looks like this:
There are three address pointer registers:
0x060 0000 for State Set 0
0x160 0000 for State Set 1
State Set 0 and 1; Read and Write
This is the LeoCross address pointer used to point to the indirectly accessed memory and registers.
0x060 0020 for State Set 0
0x160 0020 for State Set 1
State Set 0 and 1; Read and Write
This is the RAMDAC address pointer used to point to the indirectly accessed memory and registers. The RAMDAC Registers are described in Chapter 8, "RAMDAC Registers."
0x060 1010 for State Set 0
0x160 1010 for State Set 1
State Set 0 and 1; Read and Write
This is the cursor address pointer used to point to the indirectly accessed memory and registers.
There are four Cursor Function registers:
Shadow Cursor Coordinate Address
Active Cursor Coordinate Address
Cursor Color Bit Map
Cursor Enable Bit Map
The Cursor Coordinate registers accommodate the entire coordinate address consisting of 11 bits of ordinate and 11 bits of abscissa. Software accesses these registers via the shadow register; the direct path is provided for diagnostic purposes. The shadow register is transferred to the active register under Host software control using the "Cursor Control and Status Register (CSR)" (see page 7-23).
The Cursor Bit Map registers provide two 32 \xb4 32 bit maps that allow the specification of cursor shape and color. The shape is specified by the Cursor Enable Bit Map. The Cursor Color Bit Map specifies one of two color choices. It is important to note that these choices do not directly define the color, but rather they point to locations within the "Cursor Color Table" (see page 7-16). There, the colors are defined.
Figure 7-1 illustrates the relationship of map entries to display screen coordinates. Note that the byte order on the SBus, shown in the illustration, is the reverse of the byte order on the CXBus.
0x060 1018, Direct Access, State Set 0
0x160 1018, Direct Access, State Set 1
State Set 0 and 1; Read and Write
This address register specifies the screen location of the origin of the cursor bit map (comprised of the cursor enable and color planes) in display coordinates. Note that the origin is at the upper-left corner of the map. This register is also used to supply the address at which the "Trap Registers" capture pixel data.
The origin of the bit map may or may not be congruent with the place on the cursor shape that points to a specific image pixel location. If these points are not congruent, cursor software is required to calculate offsets in X and Y so that the displayed cursor shape points to the required image pixel location.
D<23 = Stereo
Specifies right (1) or left (0) view for stereo image pixel trap.
D<21:11 = Cursor Ordinate
Specifies the Y axis position of the cursor bit plane origin.
D<10:0 = Cursor Abscissa
Specifies the X axis position of the cursor bit plane origin.
0x060 101C, index = 0x40, State Set 0
0x160 101C, index = 0x40, State Set 1
State Set 0 and 1; Diagnostic Read and Write
This register is the active element in the shadow/active pair. Unlike its' shadow counterpart, it is not exposed to cursor software but is made available to diagnostic software.
D<23 = Stereo
Specifies right (1) or left (0) view for stereo image pixel trap.
D<21:11 = Cursor Ordinate
Specifies the Y axis position of the cursor bit plane origin.
D<10:0 = Cursor Abscissa
Specifies the X axis position of the cursor bit plane origin.
0x060 101C, index = 0x20 thru 0x3F for State Set 0
0x160 101C, index = 0x20 thru 0x3F for State Set 1
State Set 0 and 1; Read and Write
Specifies one of two color choices for each bit in the 32 \xb4 32 cursor bit map. Each bit in the map is defined as follows:
<-HangingPara > 0 Select color 0 of the Cursor Color Table. <-HangingPara_noSA > 1 Select color 1 of the Cursor Color Table.The actual colors resulting from these choices are defined by the contents of the Cursor Color Tables.
0x060 101C, index = 0x00 thru 0x1F for State Set 0
0x160 101C, index = 0x00 thru 0x1F for State Set 1
State Set 0 and 1; Read and Write
Specifies the shape of the cursor. Each bit in the map is defined as follows:
<-HangingPara > 0 Cursor disabled, display selected buffer: overlay, fast clear, or rbg data. <-HangingPara_noSA > 1 Cursor enabled, display selected cursor color.There are three types of Color Look Up Tables (CLUTs):
Each type of color look up table has a shadow table. Software accesses the "active" tables via their respective shadows. The shadow tables buffer LeoCommand accesses from the active tables. This allows writes to the shadow tables at any time without degrading the image on the screen. The entire contents of the shadow table is transferred to both Bank 0 and Bank 1 of the active tables under Host software control during the vertical blanking interval. Host control of the tables is done using the "VINT OPS Control and Status Registers" (see page 7-19). Two table banks are used to allow the hardware to process two pixels at the same time, thereby increasing the bandwidth. A direct path to the active CLUTs is provided for diagnostic purposes.
The active tables and their shadows share a common data format. Figure 7-2 illustrates the table format. Note that the byte order on the SBus, shown in the illustration, is the reverse of the byte order on the CXBus. Also note that Byte 0 is not used; Bytes 1, 2, and 3 are used for blue, green, and red respectively.
Figure 7-2 Color Look Up Table Data Format
State Set 0, Bank 0:
CLUT 0: 0x060 0008, index = 0x3000 thru 0x30FF (256 words)
CLUT 1: 0x060 0008, index = 0x3100 thru 0x31FF (256 words)
CLUT 2: 0x060 0008, index = 0x3200 thru 0x32FF (256 words)
State Set 0, Bank1:
CLUT 0: 0x060 0008, index = 0x3400 thru 0x34FF (256 words)
CLUT 1: 0x060 0008, index = 0x3500 thru 0x35FF (256 words)
CLUT 2: 0x060 0008, index = 0x3600 thru 0x36FF (256 words)
State Set 0, Shadow:
CLUT: 0x060 0008, index = 0x4000 thru 0x40FF (256 words)
State Set 1:
State Set 1 has a register set that is identical to those in State Set 0, except the
address is 0x160 0008 (the index in the same as in State Set 0).
State Set 0 and 1; Read and Write
See "Color Tables and Shadows" on page 7-14 for details.
State Set 0, Bank 0:
Fast Clear Color 0: 0x060 0008, index = 0x3300
Fast Clear Color 1: 0x060 0008, index = 0x3301
Fast Clear Color 2: 0x060 0008, index = 0x3302
Fast Clear Color 3: 0x060 0008, index = 0x3303
Fast Clear Color 4: 0x060 0008, index = 0x3304
Fast Clear Color 5: 0x060 0008, index = 0x3305
State Set 0, Bank 1:
Fast Clear Color 0: 0x060 0008, index = 0x3700
Fast Clear Color 1: 0x060 0008, index = 0x3701
Fast Clear Color 2: 0x060 0008, index = 0x3702
Fast Clear Color 3: 0x060 0008, index = 0x3703
Fast Clear Color 4: 0x060 0008, index = 0x3704
Fast Clear Color 5: 0x060 0008, index = 0x3705
State Set 0, Shadow:
Fast Clear Color 0: 0x060 0008, index = 0x4100
Fast Clear Color 1: 0x060 0008, index = 0x4101
Fast Clear Color 2: 0x060 0008, index = 0x4102
Fast Clear Color 3: 0x060 0008, index = 0x4103
Fast Clear Color 4: 0x060 0008, index = 0x4104
Fast Clear Color 5: 0x060 0008, index = 0x4105
State Set 1:
State Set 1 has a register set that is identical to those in State Set 0, except the
address is 0x160 0008 (the index in the same as in State Set 0).
State Set 0 and 1; Read and Write
See "Color Tables and Shadows" on page 7-14 for details.
State Set 0:
Cursor Color 0, Bank 0: 0x060 100C, index = 0x3306
Cursor Color 1, Bank 0: 0x060 100C, index = 0x3307
Cursor Color 0, Bank 1: 0x060 100C, index = 0x3706
Cursor Color 1, Bank 1: 0x060 100C, index = 0x3707
Shadow Cursor Color 0: 0x060 100C, index = 0x50
Shadow Cursor Color 1: 0x060 100C, index = 0x51
State Set 1:
Cursor Table 0, Bank 0: 0x160 100C, index = 0x3306
Cursor Table 1, Bank 0: 0x160 100C, index = 0x3307
Cursor Table 0, Bank 1: 0x160 100C, index = 0x3706
Cursor Table 1, Bank 1: 0x160 100C, index = 0x3707
Shadow Cursor Table 0: 0x160 100C, index = 0x50
Shadow Cursor Table 1: 0x160 100C, index = 0x51
State Set 0 and 1; Read and Write
See "Color Tables and Shadows" on page 7-14 for details.
There are two sets of WID LUTs:
These look up tables and shadows share a common data format. Software accesses the "active" tables via their shadows. The hardware updates the active tables by transferring the entire content of the shadow table to all five active banks under Host control during the vertical blanking interval. Host control of the tables is done using the "WID/FC CSR" (see page 7-22). Five table banks are used to allow the hardware to process five pixels at the same time, thereby increasing the bandwidth. A direct path to the active LUTs is provided for diagnostic purposes.
Figure 7-3 illustrates the table format. Note that the byte order on the SBus, shown in the illustration, is the reverse of the byte order on the CXBus.
State Set 0 (LUTs 0 through 63 in each bank):
Bank 0: 0x060 0008, index = 0x5000 thru 0x503F
Bank 1: 0x060 0008, index = 0x5100 thru 0x513F
Bank 2: 0x060 0008, index = 0x5200 thru 0x523F
Bank 3: 0x060 0008, index = 0x5300 thru 0x533F
Bank 4: 0x060 0008, index = 0x5400 thru 0x543F
Shadow: 0x060 0008, index = 0x5800 thru 0x583F
State Set 1:
State Set 1 has a register set that is identical to those in State Set 0, except the
address is 0x160 0008 (the index in the same as in State Set 0).
State Set 0 and 1; Read and Write
When the QWID code in the WID planes is zero, the PWID code in the WID planes selects one of 64 locations in the PWID Look Up Table (LUT). The PWID code is generally used for PHIGS and XGL, which need WID clipping. See "WID Look Up Table and Shadow" on page 7-17 for data format details.
State Set 0 (LUTs 0 through 15 in each bank):
Bank 0: 0x060 0008, index = 0x5040 thru 0x504F
Bank 1: 0x060 0008, index = 0x5140 thru 0x514F
Bank 2: 0x060 0008, index = 0x5240 thru 0x524F
Bank 3: 0x060 0008, index = 0x5340 thru 0x534F
Bank 4: 0x060 0008, index = 0x5440 thru 0x544F
Shadow: 0x060 0008, index = 0x5840 thru 0x584F
State Set 1:
State Set 1 has a register set that is identical to those in State Set 0, except the
address is 0x160 0008 (the index in the same as in State Set 0).
State Set 0 and 1; Read and Write
When not zero, the QWID code in the WID planes selects one of 15 locations in the QWID Look Up Table (LUT). The QWID code is generally reserved for window server use. Window system applications don't take advantage of WID clipping. See "WID Look Up Table and Shadow" on page 7-17 for data format details.
There are five VINT OPS (Vertical Interval Operations) Control and Status Registers (CSRs):
Three Image CSRs (0, 1, and 2)
WID/FC CSR
Cursor Control and Status Register (CSR)
Each of these word addressed, 8-bit registers controls transfers between an active and a shadow device. The transfer commands are executed during the next vertical blanking interval. The "WID/FC CSR" register controls both WID and Fast Clear shadow functions. Bits marked reserved return a value of zero when the register is read. At power on, these registers are reset to zero.
State Set 0:
Image 0: 0x060 0004, index = 0x1000
Image 1: 0x060 0004, index = 0x1001
Image 2: 0x060 0004, index = 0x1002
State Set 1:
Image 0: 0x160 0004, index = 0x1000
Image 1: 0x160 0004, index = 0x1001
Image 2: 0x160 0004, index = 0x1002
State Set 0 and 1; Read and Write
Specifies the availability, transfer direction, and transfer command between an Image table and its shadow.
D<2 = Device Status, Read only
<-HangingPara_noSA > 0 Available <-HangingPara_noSA > 1 Busy. This bit is cleared when the transfer is completed or if the software withdraws the transfer command.D<1 = Transfer Command
<-HangingPara_noSA > 0 No action <-HangingPara_noSA > 1 Transfer in direction specified by bit 0. This bit is cleared when the transfer is completed. Software may clear this bit to withdraw the command.D<0 = Transfer Direction
<-HangingPara_noSA > 0 Active to shadow <-HangingPara_noSA > 1 Shadow to active
0x060 0004, index = 0x1003 for State Set 0
0x160 0004, index = 0x1003 for State Set 1
State Set 0 and 1; Read and Write
Specifies the availability, transfer direction, and transfer command between both the WID and Fast Clear table and their shadows.
D<6 = FC Device Status, Read only
<-HangingPara_noSA > 0 Available <-HangingPara_noSA > 1 Busy. This bit is cleared when the transfer is completed or if the software withdraws the transfer command.D<5 = FC Transfer Command
<-HangingPara_noSA > 0 No action <-HangingPara_noSA > 1 Transfer in direction specified by bit 4. This bit is cleared when the transfer is completed. Software may clear this bit to withdraw the command.D<4 = FC Transfer Direction
<-HangingPara_noSA > 0 Active to shadow <-HangingPara_noSA > 1 Shadow to activeD<2 = WID Device Status, Read only
<-HangingPara_noSA > 0 Available <-HangingPara_noSA > 1 Busy. This bit is cleared when the transfer is completed or if the software withdraws the transfer command.D<1 = WID Transfer Command
<-HangingPara_noSA > 0 No action <-HangingPara_noSA > 1 Transfer in direction specified by bit 0. This bit is cleared when the transfer is completed. Software may clear this bit to withdraw the command.D<0 = WID Transfer Direction
<-HangingPara_noSA > 0 Active to shadow <-HangingPara_noSA > 1 Shadow to active
0x060 1014, Direct Access, State Set 0
0x160 1014, Direct Access, State Set 1
State Set 0 and 1; Read and Write
Specifies the availability, transfer direction, and transfer control between the shadow and active cursor address registers and cursor color tables. A single bit of this register acts to enable or disable the cursor display.
D<7 = Cursor Enable
Enable cursor
D<6 = Cursor Coordinate Device Status, Read only
<-HangingPara_noSA > 0 Available <-HangingPara_noSA > 1 Busy. This bit is cleared when the transfer is completed or if the software withdraws the transfer command.D<5 = Cursor Coordinate Transfer Command
<-HangingPara_noSA > 0 No action <-HangingPara_noSA > 1 Transfer in direction specified by bit 4. This bit is cleared when the transfer is completed. Software may clear this bit to withdraw the command.D<4 = Cursor Coordinate Transfer Direction
<-HangingPara_noSA > 0 Active to shadow <-HangingPara_noSA > 1 Shadow to activeD<3 = Enable/Disable Trap Register
<-HangingPara_noSA > 0 No action <-HangingPara_noSA > 1 Enable trap register trigger. This bit is cleared when hardware loads the Trap Register.D<2 = Cursor Color Table Device Status, Read only
<-HangingPara_noSA > 0 Available <-HangingPara_noSA > 1 Busy. This bit is cleared when the transfer is completed or if the software withdraws the transfer command.D<1 = Cursor Color Table Transfer Command
<-HangingPara_noSA > 0 No action <-HangingPara_noSA > 1 Transfer in direction specified by bit 0. This bit is cleared when the transfer is completed. Software may clear this bit to withdraw the command.D<0 = Cursor Color Table Transfer Direction
<-HangingPara_noSA > 0 Active to shadow <-HangingPara_noSA > 1 Shadow to activeThere are three interrupt registers:
0x060 0004, index 0x1006 for State Set 0
0x160 0004, index 0x1006 for State Set 1
State Set 0 and 1; Read and Write
The Interrupt Enable Mask register allows the host to select the events that generate interrupts. Writing a logical 1 to a location within this register enables the corresponding CSR status bits to participate in the generation of an interrupt. Writing a logical zero prevents participation. This register is implemented as a single, word addressed, 8-bit register, which may be read or written by the host. Bits marked reserved return a value of zero when the register is read. At power on, the register is reset to zero.
ALL FIELDS
<-HangingPara_noSA > 0 Disable interrupt <-HangingPara_noSA > 1 Enable interrupt
0x060 0004, index 0x1005 for State Set 0
0x160 0004, index 0x1005 for State Set 1
State Set 0 and 1; Read and Diagnostic Write
When the last scheduled vertical interval operation reaches completion, LX hardware compares the content of the Interrupt Enable Mask register with the state of the various controlling state machines. If the comparison shows that any or all of the completed operations are allowed to generate an interrupt, LX hardware marks the appropriate locations in the Interrupt Event register and sets the VINT bit to a logical 1. This bit is propagated to the Leo Command chip, via a dedicated connection, where it causes the vertical retrace active bit of the Leo Command port status register to be set. This, in turn, generates an interrupt. The VINT bit remains set until the host clears all of the bits of the Interrupt Event register, at which time, LX hardware automatically resets it.
The Interrupt Event register is implemented as a single, word addressed, 8-bit register, which may be read (or written for diagnostic convenience) by the host. Bits marked reserved return a value of zero when the register is read. At power on, the register is reset to zero.
ALL FIELDS
<-HangingPara_noSA > 0 Event did not occur <-HangingPara_noSA > 1 Event occurred
0x060 0004, index 0x1007 for State Set 0
0x160 0004, index 0x1007 for State Set 1
State Set 0 and 1; Read and Write
The Interrupt Event register is not directly cleared by host software in order to avoid collisions between clearing operations and changes in the state of Interrupt Event register bits. The Interrupt Clear Mask register is provided for this purpose. Each bit in this register corresponds to the bits of the Interrupt Event register. Writing a logical 1 to a bit in the Interrupt Clear Mask register causes LX hardware to reset the corresponding bit in the Interrupt Event register. This action occurs only at the time the clear mask is written. This is because the Interrupt Clear Mask register is actually a phantom register that does not retain state but rather serves as an addressed port through which the Interrupt Event register is cleared.
ALL FIELDS
<-HangingPara_noSA > 0 No action <-HangingPara_noSA > 1 Clear interrupt eventThere are two trap registers:
Trap, Bank 0 (Even) (even)
Trap, Bank 1 (Odd) (odd)
These two registers capture pixel data at the next even and odd location after the location specified by the "Shadow Cursor Coordinate Address" register (see page 7-11). When the "Cursor Enable Bit Map" (see page 7-13) contains "0" in the first two locations, the image rgb data is trapped. When the map contains "1" in these two locations, the first two locations of the "Cursor Color Bit Map" are trapped.
0x060 101C, index = 0x80 for State Set 0
0x160 101C, index = 0x80 for State Set 1
State Set 0 and 1; Read only
This register traps a pixel of data for the an even address.
D<27 = Odd Field
<-HangingPara_noSA > 0 Indicates an even field (PAL or NTSC) <-HangingPara_noSA > 1 Indicates an odd field
D<26 = Composite Sync
Indicates the level of the composite synch signal at this pixel location.
D<25 = Composite Blank
Indicates the level of the composite blank signal at this pixel location.
D<26 = Right Field
<-HangingPara_noSA > 0 Indicates a left stereo field <-HangingPara_noSA > 1 Indicates a right stereo field
D<23:16 = Blue
Indicates the value of the blue color for this pixel.
D<23:16 = Green
Indicates the value of the green color for this pixel.
D<23:16 = Red
Indicates the value of the red color for this pixel.
0x060 101C, index = 0x81 for State Set 0
0x160 101C, index = 0x81 for State Set 1
State Set 0 and 1; Read only
Usage
This register traps a pixel of data for an odd address. See the "Trap, Bank 1 (Odd)" register for Bit Field details.
There are three EXmach registers:
0x060 0004, index = 0x201F for State Set 0
0x160 0004, index = 0x201F for State Set 1
State Set 0 and 1; Read and Write
This is the Image start address for the Image/WID Extraction Machine.
0x060 0004, index = 0x201E for State Set 0
0x160 0004, index = 0x201E for State Set 1
State Set 0 and 1; Read and Write
This is the WID start address for the Image/WID Extraction Machine.
0x060 0004, index = 0x201D for State Set 0
0x160 0004, index = 0x201Dfor State Set 1
State Set 0 and 1; Read and Write
This is the loop count for the Image/WID Extraction Machine. The loop count controls a function of this state machine.
There are eight equalization registers:
Equalization Pulse Start Address
Equalization Pulse End Address
Equalization Interval 1 Start Address
Equalization Interval 1 End Address
Equalization Interval 2 Start Address
Equalization Interval 2 End Address
Serration Pulse Start Address
Serration Pulse End Address
0x060 0004, index = 0x2014 for State Set 0
0x160 0004, index = 0x2014 for State Set 1
State Set 0 and 1; Read and Write
This is the pixel address that lets the synch generator produce the beginning of the equalization pulse.
0x060 0004, index = 0x2013 for State Set 0
0x160 0004, index = 0x2013 for State Set 1
State Set 0 and 1; Read and Write
This is the pixel address that lets the synch generator disable the equalization pulse.
0x060 0004, index = 0x2016 for State Set 0
0x160 0004, index = 0x2016 for State Set 1
State Set 0 and 1; Read and Write
This is the line address that lets the synch generator start the equalization interval.
0x060 0004, index = 0x2015 for State Set 0
0x160 0004, index = 0x2015 for State Set 1
State Set 0 and 1; Read and Write
This is the line address that lets the synch generator finish the equalization interval.
0x060 0004, index = 0x2018 for State Set 0
0x160 0004, index = 0x2018 for State Set 1
State Set 0 and 1; Read and Write
This is the pixel address that lets the synch generator start the equalization interval.
0x060 0004, index = 0x2017 for State Set 0
0x160 0004, index = 0x2017 for State Set 1
State Set 0 and 1; Read and Write
This is the pixel address that lets the synch generator finish the equalization interval.
0x060 0004, index = 0x201B for State Set 0
0x160 0004, index = 0x201B for State Set 1
State Set 0 and 1; Read and Write
This is the pixel address that lets the synch generator produce the beginning of the serration pulse.
0x060 0004, index = 0x201A for State Set 0
0x160 0004, index = 0x201Afor State Set 1
State Set 0 and 1; Read and Write
This is the pixel address that lets the synch generator disable the serration pulse.
There are six vertical registers:
Vertical Counter (Diagnostic Read)
VSynch Start Address
VSynch End Address
VBlank Start Address
VBlank End Address
Vertical Counter Size
0x060 0004, index = 0x2012, State Set 0
0x160 0004, index = 0x2012, State Set 1
State Set 0 and 1; Read only
This is a diagnostic read port that provides access to the current count in the Vertical Counter of the timing generator. Data validity is guaranteed only when the Vertical Counter is operated in the diagnostic mode.
0x060 0004, index = 0x2011 for State Set 0
0x160 0004, index = 0x2011 for State Set 1
State Set 0 and 1; Read and Write
This is the line address that lets the synch generator produce the beginning of the vertical synch pulse.
0x060 0004, index = 0x2010 for State Set 0
0x160 0004, index = 0x2010 for State Set 1
State Set 0 and 1; Read and Write
This is the line address that lets the synch generator disable the vertical synch pulse.
0x060 0004, index = 0x200F for State Set 0
0x160 0004, index = 0x200F for State Set 1
State Set 0 and 1; Read and Write
This is the line address that lets the synch generator produce the beginning of the vertical blanking pulse.
0x060 0004, index = 0x200E for State Set 0
0x160 0004, index = 0x200E for State Set 1
State Set 0 and 1; Read and Write
This is the line address that lets the synch generator disable the vertical blanking pulse.
0x060 0004, index = 0x200D for State Set 0
0x160 0004, index = 0x200Dfor State Set 1
State Set 0 and 1; Read and Write
A vertical counter produces the number of scan-lines in a frame. When its value matches the content of this register and the last pixel of that line has occurred, the vertical counter resets itself in the next clock cycle.
There are six horizontal registers:
Horizontal Counter (Diagnostic Read)
HSynch Start Address
HSynch End Address
HBlank Start Address
HBlank End Address
Horizontal Counter Size
0x060 0004, index = 0x200A for State Set 0
0x160 0004, index = 0x200A for State Set 1
State Set 0 and 1; Read only
This is a diagnostic read port that provides access to the current count in the Horizontal Counter of the timing generator. Data validity is guaranteed only when the Horizontal Counter is operated in the diagnostic mode.
0x060 0004, index = 0x200C for State Set 0
0x160 0004, index = 0x200C for State Set 1
State Set 0 and 1; Read and Write
This is the pixel address that lets the synch generator produce the beginning of the horizontal synch pulse. The pixel address to load into this register must be the divisible-by-10 number that is the lower number of the nearest to the desire number. For example, if the desired address is 384, the number to program is 380. LeoCross produces the desired start-pulse edge at the desired point for the RAMDAC.
0x060 0004, index = 0x200B for State Set 0
0x160 0004, index = 0x200B for State Set 1
State Set 0 and 1; Read and Write
This is the pixel address that lets the synch generator disable the horizontal synch pulse. Same procedure as the above register.
0x060 0004, index = 0x2009 for State Set 0
0x160 0004, index = 0x2009 for State Set 1
State Set 0 and 1; Read and Write
This is the pixel address that lets the synch generator produce the beginning of the horizontal blanking pulse
0x060 0004, index = 0x2008 for State Set 0
0x160 0004, index = 0x2008 for State Set 1
State Set 0 and 1; Read and Write
This is the pixel address that lets the synch generator disable the horizontal blanking pulse
0x060 0004, index = 0x2007 for State Set 0
0x160 0004, index = 0x2007 for State Set 1
State Set 0 and 1; Read and Write
A horizontal counter produces the pixel address. When the value of the horizontal counter matches the content of this register, the horizontal counter resets itself in the next clock cycle. External clock logic must provide the synchronization of the edges between the pix_clk/5 and pix_clk/2 clocks at the start of every horizontal line.
There are four configuration registers:
Configuration Register Zero
Configuration Register One
Configuration Register Two
Configuration Register Three
0x060 0004, index = 0x2003 for State Set 0
0x160 0004, index = 0x2003 for State Set 1
State Set 0 and 1; Read and Write
Video Timing Configuration Register. This is the control register that sets functionality of the LeoCross chip.
D<15 = Frame Counter Enable
Enable the Frame Counter.
D<14 = DRAM Refresh Counter Disable
Disable the DRAM Refresh Counter.
D<13 = Interlaced First Field to Xfer
<-HangingPara_noSA > 0 Instructs LeoDraw to use the Screen Start Address Even and Screen Offset Even registers for VRAM transfer cycles <-HangingPara_noSA > 1 Instructs LeoDraw to use the Screen Start Address Odd and Screen Offset Odd registers for VRAM transfer cyclesD<12 = 1280 \xb4 1024 Enable
<-HangingPara_noSA > 0 Disable 1280 \xb4 1024; allows for other monitor resolutions <-HangingPara_noSA > 1 Enable 1280 \xb4 1024; provides optimized acceleration for the standard Leo MonitorD<11 = Stereo Shutter Polarity
<-HangingPara_noSA > 0 Select left field <-HangingPara_noSA > 1 Select right fieldD<10 = Stereo Monitor
<-HangingPara_noSA > 0 Select non-stereo monitor <-HangingPara_noSA > 1 Select stereo monitorD<9 = Stereo First Field to Xfer
<-HangingPara_noSA > 0 Instructs LeoDraw to use the Screen Start Address Left and Screen Offset Left registers for VRAM transfer cycles <-HangingPara_noSA > 1 Instructs LeoDraw to use the Screen Start Address Right and Screen Offset Right registers for VRAM transfer cyclesD<8 = Interlaced Monitor
<-HangingPara_noSA > 0 Select non-interlaced monitor <-HangingPara_noSA > 1 Select interlaced monitor; the actual type of interlaced monitor (PAL or NTSC) is determined by the values loaded into the video timing registersD<7 = Interlaced First Field
<-HangingPara_noSA > 0 Select odd field first <-HangingPara_noSA > 1 Select even field first
D<6 = Equalization Pulse Enable
Enable Equalization Pulse.
D<5 = Serration Pulse Enable
Enable Serration Pulse.
D<4 = Synch On Video
Select Synch On Video; inhibits external composite synch.
D<3 = Video Enable
<-HangingPara_noSA > 0 Blank the screen <-HangingPara_noSA > 1 Enable videoD<2 = Composite Blank Polarity
<-HangingPara_noSA > 0 Active high signal <-HangingPara_noSA > 1 Active low signal
D<1 = Sync Enable
Enable external composite sync.
D<0 = Composite Sync Polarity
<-HangingPara_noSA > 0 Active high signal <-HangingPara_noSA > 1 Active low signal
0x060 0004, index = 0x2004 for State Set 0
0x160 0004, index = 0x2004 for State Set 1
State Set 0 and 1; Read and Write
Diagnostic Control Register. This is another test-control register.
The registers controlled by bits 1 through 5 (DRAM Refresh Counter, Vertical Counter, Horizontal Counter, WID Transfer Counter, and CLUT Transfer Counter) are split into 4-bit sections to simplify testing all count values. During testing, each section of a register is increminated by the controlling bit, checked for the right count, and then incremented and check again until the count reaches 0xFF. Thus, an entire counter can be checked with just 16 counts. To test the final counter path, bit 0 (Diagnostic enable) is turned off and the system signals are allowed to increment the register to zero.
The registers controlled by bits 6, 7, and 10 (LeoCross Address Pointer, Cursor Pointer, and Video Frame Counter) are not split into 4-bit sections. During testing, a register is incremented by the controlling bit, checked for the right count, and then incremented and check again until the count reaches 0x100. Then the registers is loaded with 1FF, incremented and checked, loaded with 2FF, incremented and checked, and so on until the count reaches 0x1FFFF. These registers are thus checked in 4-bit sections until the all count values have been checked.
D<14 = Soft System Reset
Resets all LeoCross registers except the "LeoCross Address Pointer" and
"Cursor Address Pointer."
D<13 = Synthesized Right Field
Force a right field transfer (Stereo) from LeoDraw now
D<12 =Synthesized Odd Field
Force an odd field transfer (Interlaced) from LeoDraw now
D<11 = Synthesized Horiz Synch
Force a horizontal synch pulse to start now
D<10 = Increment Frame Counter
Adds one to the "Video Frame Counter" if bit 0 (Diagnostic Enable) is set.
Must be set to "0" and then back to "1" to increment the counter again.
D<9 = Synthesized Vertical Blank
Force a vertical blank pulse to start now
D<8 = Active CLUT Enable
Enable direct read and write access to the Active Color Look Up Table.
D<7 = Increment Cursor Addr Pointer
Adds one to the "Cursor Address Pointer" if bit 0 (Diagnostic Enable) is set.
Must be set to "0" and then back to "1" to increment the counter again.
D<6 = Increment LX Addr Pointer
Adds one to the "LeoCross Address Pointer" if bit 0 (Diagnostic Enable) is set.
Must be set to "0" and then back to "1" to increment the counter again.
D<5 = Increment CLUT Transfer Counter
Adds one to the "CLUT Transfer Counter" if bit 0 (Diagnostic Enable) is set.
Must be set to "0" and then back to "1" to increment the counter again.
D<4 = Increment WID Transfer Counter
Adds one to the "WID Transfer Counter" if bit 0 (Diagnostic Enable) is set.
Must be set to "0" and then back to "1" to increment the counter again.
D<3 = Increment Horiz Counter
Adds one to the "Horizontal Counter" if bit 0 (Diagnostic Enable) is set. Must
be set to "0" and then back to "1" to increment the counter again.
D<2 = Increment Vert Counter
Adds one to the "Vertical Counter" if bit 0 (Diagnostic Enable) is set. Must be
set to "0" and then back to "1" to increment the counter again.
D<1 = Increment DRAM Refresh Count
Adds one to the "DRAM Refresh Counter" if bit 0 (Diagnostic Enable) is set.
Must be set to "0" and then back to "1" to increment the counter again.
D<0 = Diagnostic Enable
Enable the diagnostic test counters.
0x060 0004, index = 0x2005 for State Set 0
0x160 0004, index = 0x2005 for State Set 1
State Set 0 and 1; Read and Write
Set to 0 to issue a software reset for the LeoCross pixel clock. This bit also resets all LeoCross registers that increment on the pixel clock.
0x060 0004, index = 0x2006 for State Set 0
0x160 0004, index = 0x2006 for State Set 1
State Set 0 and 1; Read and Write
This register is used to test various LeoCross video timing registers.
D<5 = Vertical Sync Test Comparator
Set to 1 between the "VSynch Start Address" and the "VSynch End Address."
D<4 = Equalization Interval 2 Test Comparator
Set to 1 between the "Equalization Interval 2 Start Address" and the
"Equalization Interval 2 End Address."
D<3 = Equalization Interval 1 Test Comparator
Set to 1 between the "Equalization Interval 1 Start Address" and the
"Equalization Interval 1 End Address."
D<2 = Vertical Blank Test Comparator
Set to 1 between the "VBlank Start Address" and the "VBlank End Address."
D<1 = Horizontal Blank Test Comparator
Set to 1 between the "HBlank Start Address" and the "HBlank End Address."
D<0 = Composite Sync Test Comparator
Set to 1 between the values specified in enabled start and stop register:
Set bit 1 of "Configuration Register Zero" to enable "HSynch Start Address" and "HSynch End Address."
Set bit 5 of "Configuration Register Zero" to enable "Serration Pulse Start Address" and "Serration Pulse End Address."
Set bit 6 of "Configuration Register Zero" to enable "Equalization Pulse Start Address" and "Equalization Pulse End Address."
There are eight unclassified registers:
LX Chip Code
Monitor ID
DRAM Refresh Count
DRAM Refresh Counter
Video Frame Counter
Video Clock Generator
Stereo Shutter Switch
WID Transfer Counter
CLUT Transfer Counter
0x060 0004, index = 0x2000 for State Set 0
0x160 0004, index = 0x2000 for State Set 1
State Set 0 and 1; Read and Write
This is a 32-bit register that uniquely identifies the LeoCross chip.
D<31:28 = VERSION
Specifies the version of the LeoCross chip.
D<27:12 = DEVICE IDENTIFICATION
The device identification code for the LeoCross chip.
D<11:1 = JED MANUFACTURER CODE
The JED manufacturer code assigned to Sun Microsystems or vender.
D<0 = 1
Always in the high state.
0x060 0004, index = 0x2001 for State Set 0
0x160 0004, index = 0x2001 for State Set 1
State Set 0 and 1; Read only (Diagnostic Write)
LeoCross latches the value of the monitor ID pins in this register. This field is coded as follows:
0 1024 \xb4 768 at 76 Hz
1 1152 \xb4 900 at 66 Hz
2 1280 \xb4 1024 at 76 Hz
3 1152 \xb4 900 at 66 Hz
4 1280 \xb4 1024 at 67 Hz
5 1152 \xb4 900 at 66 Hz
6 1152 \xb4 900 at 76 Hz
7 No Monitor (defaults to 1152 \xb4 900 at 66 Hz)
0x060 0004, index = 0x2002 for State Set 0
0x160 0004, index = 0x2002 for State Set 1
State Set 0 and 1; Read and Write
See "DRAM Refresh Counter" for details.
0x060 0004, index = 0x2024 for State Set 0
0x160 0004, index = 0x2024 for State Set 1
State Set 0 and 1; Read only
After a count is written into the "DRAM Refresh Count" register, it is loaded into this counter at the next rising edge of the system clock; and the counter counts down at each rising edge of the system clock. While the value of the counter is 0x0, a single-clock-cycle pulse is generated at the refresh_req pin. At the next clock edge, the value from the "DRAM Refresh Count" register is re- loaded into the counter, and the operation repeats.
0x060 200C (direct) for State Set 0
0x160 200C (direct) for State Set 1
State Set 0 and 1; Read and Write
This register is used by the software to time an interval between two events. For example, when doing animation using double buffering, if it takes a maximum of four frames to render a buffer, you can do smooth animation by switching buffers every four frames.
0x060 0004, index = 0x2027 for State Set 0
0x160 0004, index = 0x2027 for State Set 1
State Set 0 and 1; Read and Write
This register selects the Synthesizer frequency and the LX prescale value.
D<7:6 = Prescale Selection (see Table 7-4 on page 7-55)
<-HangingPara_noSA > 00 Divide by 1 <-HangingPara_noSA > 01 Divide by 2 <-HangingPara_noSA > 10 Divide by 4 <-HangingPara_noSA > 11 Reserved
D<5 = Synthesizer Strobe
Strobes the address and data bits into the frequency synthesizer. This bit is set
to 1 to load the address into the synthesizer, then set to 0 to load the data into
the selected address.
D<3:0 = Address and Data
The synthesizer uses 13 registers to define the pixel clock frequency. The
registers are described in Table 7-2.
Table 7-2 Pixel Clock Synthesizer Registers
-------------------------------------------------------------------------------------
Register Bits Register Description No. Bits -------------------------------------------------------------------------------------
0 0 - 3 R(0) - R(3) Reference divider (R) modulus control bits 0 - 3.
Modulus = value + 1
1 0 - 2 R(4) - R(6) Reference divider (R) modulus control bits 4 - 6.
2 0 - 3 A(0) - A(3) Feedback divider "A" counter control. When set to 0,
modulus = 7. Otherwise, modulus = 7 for value
underflows of the prescaler, and modulus = 6
thereafter until "M" counter underflows.
3 0 - 3 M(0) - M(3) Feedback divider "M" counter control bits 0 - 3.
Modulus = value + 1.
4 0 - 1 M(4) - M(5) "M" counter control bits 4 - 5.
4 2 - 3 Not used for Leo.
5 0 - 3 Not used for Leo.
6 0 - 3 Not used for Leo.
7 0 - 3 Not used for Leo.
8 3 Not used for Leo.
8 0 - 2 V(0) - V(2) VCO gain. See Table 7-3.
9 0 - 1 P(0) - P(1) Phase detector gain. Set to 1 for Leo.
9 2 - 3 Not used for Leo.
11 0 - 1 S(0) - S(1) Post scaler. See Table 7-4. Normally set to 0 for Leo.
12 0 - 3 Not used for Leo.
15 3 PDRSTEN Phase-detector reset enable. Set to 0 on Leo.
-------------------------------------------------------------------------------------
After power up, the synthesizer requires 32 register writes for new programming to become effective. Since the synthesizer has only 13 registers, programming requires 19 dummy writes. The dummy writes can be to register 13 or 14 (unused registers).
The synthesizer frequency is determined by the following equation:
where
F
F
N = Feedback divider
R = Reference divider
The reference divider, R, may be programmed for any modulus from 1 to 128 in steps of 1.
The feedback divider may be programmed for any modulus from 37 through 448 in steps of 1. The feedback divider uses a dual-modulus prescaler, the A and M counters, that allows the programmable counters to operate at low frequencies. The A and M counters are programmable via registers 2 and 3.
The equation for determining the feedback divider, N, is:
N = [6(M + 1)] + A
except when A = 0, then:
N = 7(M + 1)
The VCO gain is also programmable, in MHz/volt, as shown in Table 7-3.
Table 7-3 VCO Gain
---------------------------
V(2) V(1) V(0) VCO Gain (MHz/Volt) ---------------------------
1 0 0 30
1 0 1 45
1 1 0 60
1 1 1 80
---------------------------
The post scaler may be used as shown in Table 7-4.
Table 7-4 Post Scaler
---------------------------
S(1) S(2) Description ---------------------------
0 0 Post-scaler = 1
0 1 Post scaler = 2
1 0 Post scaler = 4
1 1 Not used
---------------------------
Table 7-4 shows the standard synthesizer frequencies used in Leo.
--------------------------------------------------------
Prescale Synthesizer Resolution Selection Frequency (Bits 7:6) (MHz) --------------------------------------------------------
00 12.272727 640 \xb4 480 @ 60 Hz (NTSC)
00 14.75 768 \xb4 576 @ 50 Hz (PAL)
10 65.00 1024 \xb4 768 @ 60 Hz (VGA)
10 84.375 1024 \xb4 768 @ 76 Hz (VGA)
10 93.0 1152 \xb4 900 @ 66 Hz
10 99.9 960 \xb4 680 @ 108 Hz (stereo)
10 101.25 960 \xb4 680 @ 112 Hz (stereo)
10 105.75 1152 \xb4 900 @ 76 Hz
10 117.0 1280 \xb4 1024 @ 67 Hz
10 135.0 1280 \xb4 1024 @ 76 Hz
--------------------------------------------------------
0x060 0004, index = 0x2021 for State Set 0
0x160 0004, index = 0x2021 for State Set 1
State Set 0 and 1; Read and Write
The stereo shutter switch register specifies the line position where the left and right views are toggled. It is synchronized with the start of the horizontal synch pulse (not adjusted).
0x060 0004, index = 0x2023 for State Set 0
0x160 0004, index = 0x2023 for State Set 1
State Set 0 and 1; Diagnostic Read only
This is a read port into the WID Transfer Counter that is used to address the tables during transfers between the WID LUTs and their shadows. It is used only by diagnostics to verify that the counter is operating properly. The diagnostic increments the counter using bit 4 of "Configuration Register One."
0x060 0004, index = 0x2022 for State Set 0
0x160 0004, index = 0x2022 for State Set 1
State Set 0 and 1; Diagnostic Read only
This is a read port into the CLUT Transfer Counter that is used to address the tables during transfers between the Image CLUTs and their shadows. It is used only by diagnostics to verify that the counter is operating properly. The diagnostic increments the counter using bit 5 of "Configuration Register One."
