This chapter describes the CX Bus.
The CX Bus, shown in Figure 5-1, is an eight-bit bus that interfaces LeoCommand with LeoCross, the Output RAMDAC, and the Boot PROM. LeoCommand controls CX Bus accesses. The LeoCross and Output RAMDAC devices contain several registers and memories used to program the video timing generator and to control the cursor, as well as the transformation of pixel data. The CX Bus also serves the subsidiary purpose of conveying the data component of Boot PROM transactions.
The CX Bus is bidirectional, used to communicate between LeoCommand and the Boot PROM, LeoCross, and Output RAMDAC. LeoCommand serves as the bus master; the other devices are bus slaves. The bus master initiates and regulates all transactions. The slaves are only capable of responding.
Figure 5-1 CX Bus Block Diagram
The bus between LeoCommand and LeoCross operates in a synchronous fashion. Information on the bus is not clocked by a strobe signal (chip enable) but rather by the local clock. Data on the bus is guaranteed to be stable prior to the rising clock edge subsequent to the assertion of the data. Similarly, control signals do not cause actions immediately upon assertion. The control signals are sampled by the system clock and the intended actions are produced on subsequent clock boundaries.
The Output RAMDAC has an asynchronous interface. The LeoCommand CX Bus controller performs the necessary adaptation between synchronous and asynchronous transfers.
The slave devices on the CX Bus have different response times. LeoCross responds more quickly than the Output RAMDAC. The Output RAMDAC responds more quickly than the Boot PROM. Additionally, the Output RAMDAC and Boot PROM do not produce a signal that indicates the completion of a transaction. Consequently, LeoCommand regulates bus timing, dependent on the slave device being accessed.
The CX Bus is limited to transfers of one byte at a time. Bus slave devices, however, have data widths that vary between one and four bytes. Master and slave controllers act as either senders or receivers of data. Senders decompose multi-byte transfers into two or more single-byte CX Bus transfers. Receivers re-compose these transfers into a single, multi-byte word.
The CX Bus interfaces to LeoCross and the Output RAMDAC use an address auto-increment mechanism in both the byte and word dimensions. This technique is used to improve the bus band-width, which is improved by obviating the need to transfer word address and datum pairs. LeoCommand transfers a single base address, or index, followed by multiple data transfers that may consist of multiple bytes per word and multiple words. The address increment mechanism automatically adjusts the address in both the byte and word dimensions.
This technique does not preclude the use of the word address and datum pair access mode. In fact, not all devices within LeoCross and the Output RAMDAC use the incrementing mechanism. Therefore, there are two access strategies: direct and indirect. These two strategies are differentiated by the CX Bus CX_C<2:0 signals (which are derived from the SBus address). This addressing is completely hardware controlled; direct and indirect accesses are otherwise transparent to the host software.
CX Bus direct accesses use neither word dimension auto-incrementing nor an index to specify the entry location. The entry location is specified directly by control signals CX_CTL<2:0 (see Table 5-2 on page 5-6).
Indirect byte accesses are subdivided into two types: register and table. Both access types use dimension auto-incrementing, but only the table type uses byte and word dimension auto-incrementing. This distinction is imposed by the Output RAMDAC to allow read-modify-write operations on registers. The distinction is applied to LeoCross only to maintain interface uniformity.
Both register and table accesses require a preamble phase that consists of a direct write to the address pointer. The data field of this write contains either a register address or an index into a table.
Register type accesses consist of two SBus cycles, the previously-mentioned preamble being the first cycle. The second SBus cycle comprises the data transfer.
The receiving device uses byte dimension auto-incrementing. Upon completion of a word transfer, the receiving device resets the byte dimension address pointer - it does not increment the word dimension pointer.
Table type accesses may consist of a minimum of two SBus cycles or a maximum of n SBus cycles, where n is defined by the depth of the table being accessed. As with register accesses, the first SBus cycle is the preamble and subsequent cycles comprise data transfers.
The receiving device uses byte dimension auto-incrementing. Upon completion of a word transfer, the receiving device resets the byte dimension address pointer and increments the word dimension address pointer.
Table 5-1 summarizes the CX Bus signals.
Table 5-1 CX Bus Signals
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Signal Name No. Pins I/O Type Description -------------------------------------------------------------------------------------------------------------------
CX_DAT<7:0'> 8 I/O Tri-state Address and data bus.
PROM_CS_L 1 O Bi-state Boot PROM chip enable.
LX_CE_L 1 O Bi-state LeoCross chip enable.
CX_DAC_CS_L 1 O Bi-state Output RAMDAC chip enable.
CX_R_WL 1 O Bi-state Transaction direction control (read or write).
CX_CTL<2:0'> 3 O Bi-state Control bits.
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These are the eight data and address lines for the bus. LeoCommand uses this bus to load the LeoCross lookup tables and control registers and the Output RAMDAC color tables and command registers.
The chip enable line for the Boot PROM. When asserted, the Boot PROM enables its data onto the CX Bus data lines. Although not directly involved with the CX Bus, this device is mentioned here to emphasize the fact that LeoCommand must produce this signal and because the CX Bus data lines are used to convey Boot PROM data. The Boot PROM address lines and the remaining control lines reside on the CD Bus.
The chip enable line for LeoCross. When asserted, LeoCross monitors the CX Bus for requested activities.
The chip enable line for the Output RAMDAC. When asserted, the Output RAMDAC monitors the CX Bus for requested activities.
Transaction direction control (read or write). When this signal is low (write), LeoCommand drives the CX Bus. The enabled device takes the bus information and performs a write operation to the specified register or table.
When this signal is high, LeoCross performs the read cycle. Within a specified number of clock cycles, LeoCross or the Output RAMDAC drives its requested data, set by its internal address register, onto the CX Bus.
Control bits. These signals are derived from the SBus address and are used to differentiate between direct and indirect accesses. They also provide the direct access device address. The exact meaning of these control bits depends on whether LeoCommand is accessing the Output RAMDAC or LeoCross, as defined by the LX_CE and CX_DAC_CS_L signals, as shown in Table 5-2.
Table 5-2 CX Bus Control Signal Decoding
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Select C2 C1 C0 Description Access -------------------------------------------------------
LeoCross 0 0 0 LeoCross address pointer Direct
LeoCross 0 0 1 LeoCross control registers Indirect
LeoCross 0 1 0 LeoCross color tables Indirect
LeoCross 0 1 1 Video frame counter Direct
LeoCross 1 0 0 Cursor address pointer Direct
LeoCross 1 0 1 Cursor CSR Direct
LeoCross 1 1 0 Shadow cursor address Direct
LeoCross 1 1 1 Cursor functions Indirect
RAMDAC 0 0 0 RAMDAC address pointer Direct
RAMDAC 0 0 1 RAMDAC color table Indirect
RAMDAC 0 1 0 RAMDAC control register Indirect
RAMDAC 0 1 1 RAMDAC mode register Direct
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Bus signal timing differs as a function of the selected slave. Although LeoCommand adapts timing to suit the requirements of the Output RAMDAC, the RAMDAC still uses the chip-enable to register commands and data. This means that every transfer must be accompanied by a transition of the chip enable signal. This is not true for LeoCross, which uses the local clock for that purpose. Consequently, multiple transfers, with chip enable asserted, are allowed and band-width is improved. The following figures show the relationship of the bus signals and how they differ for LeoCross and Output RAMDAC accesses.
The following figures describe LeoCross accesses:
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Figure No. Title Page ------------------------------------------------------------
Figure 5-2 LeoCross Single Byte Direct Write page 5-8
Figure 5-3 LeoCross Single Byte Direct Read page 5-8
Figure 5-4 LeoCross Multiple Byte Direct Write page 5-9
Figure 5-5 LeoCross Multiple Byte Direct Read page 5-9
Figure 5-6 LeoCross n Byte Indirect Write page 5-10
Figure 5-7 LeoCross n Byte Indirect Read page 5-11
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Figure 5-2 LeoCross Single Byte Direct Write
Figure 5-3 LeoCross Single Byte Direct Read
Figure 5-4 LeoCross Multiple Byte Direct Write
Figure 5-5 LeoCross Multiple Byte Direct Read
Figure 5-6 LeoCross n Byte Indirect Write
Figure 5-7 LeoCross n Byte Indirect Read
The following figures describe Output RAMDAC accesses:
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Figure No. Title Page ----------------------------------------------------------------
Figure 5-8 Output RAMDAC Single Byte Direct Write page 5-12
Figure 5-9 Output RAMDAC Single Byte Direct Read page 5-12
Figure 5-10 Output RAMDAC n Byte Indirect Write page 5-13
Figure 5-11 Output RAMDAC n Byte Indirect Read page 5-14
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Figure 5-8 Output RAMDAC Single Byte Direct Write
Figure 5-9 Output RAMDAC Single Byte Direct Read
Figure 5-10 Output RAMDAC n Byte Indirect Write
Figure 5-11 Output RAMDAC n Byte Indirect Read
The CX Bus operates at either CMIS or TTL levels without termination of bus signals. This is achieved by limiting the distance the signal must travel and by selection of bus drivers for appropriate current characteristics.
The conductors that convey the bus signals are physically realized as standard copper/epoxy laminate stripline or micro-strip transmission lines. Table 5-3 lists the electrical characteristics of these conductors. Figure 5-12 shows the timing parameters of the bus signals.
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Signal Name Figure 5-12 Parameter Min Typ Max Load Units Reference --------------------------------------------------------------------------------------------------
All Conductor length 12 Inches
Lateral conductor spacing 4X Width
Zo, Conductor impedance 65 110 Ohms
Co, Intrinsic capacitance 16 35 pF/ft
Td, Intrinsic delay 1.7 2.3 ns/ft
Rt, Terminating resistance o Ohms
Clock 1 1/f, Period 40 ns
2 tskew, the reference is LC -2 +2 ns
LX_CE_L 3 tpLH, low to high transition 50 pF
relative to clock
CX_DAC_CS
CX_CTL<2:0'>
10 15 ns
4 tpHL, high to low transition 10 15 ns
relative to clock
5 tsu, set up time relative to clock 5 ns
6 thd, hold time relative to clock 10 ns
tr, tf, rise and fall time relative to 4 ns
20% and 80% points
CX_DAT<7:0'> 7 tpData, data valid relative to clock 100 pF
20 ns
8 tpLZ, transition from high to low 15 ns
impedance state
9 tpHZ, transition from low to high 15 ns
impedance state
10 tsu, set up time relative to clock 5 ns
11 thd, hold time relative to clock 10 ns
tr, tf, rise and fall time relative to 4 ns
20% and 80% points.
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Figure 5-12 CX Bus Signal Parameter Names
