.include "reg.s11"
	.include "cons.s11"
. = 200
	jmp	start
. = 1000
stacktop:
start:
	mov	#stacktop-4,sp
	jsr	pc,crlf
	mov	#300,2(sp)
	mov	#140,(sp)
	jsr	pc,trysub
	mov	#0x8001,2(sp)
	mov	#1,(sp)
	jsr	pc,trysub
	mov	#0x8000,2(sp)
	mov	#1,(sp)
	jsr	pc,trysub
	mov	#5,2(sp)
	mov	#7,(sp)
	jsr	pc,trysub
	mov	#0x7ffe,2(sp)
	mov	#0x8002,(sp)
	jsr	pc,trysub
	mov	#1,2(sp)
	mov	#1,(sp)
	jsr	pc,trysub
	halt
	br	start
trysub:
	clr	-(sp)
	jsr	pc,crlf
	mov	6(sp),-(sp)
	jsr	pc,print6
	jsr	pc,crlf
	mov	6(sp),(sp)
	jsr	pc,print6
	jsr	pc,crlf
	mov	10(sp),(sp)
	sub	6(sp),(sp)
	mov	@#reg_psw,2(sp)
	jsr	pc,print6
	jsr	pc,crlf
	tst	(sp)+
	jsr	pc,printcc
	jsr	pc,crlf
	tst	(sp)+
	rts	pc
printcc:
	mov	#nzvc_str,-(sp)
	jsr	pc,puts
	mov	#'0,(sp)
	bit	#reg_psw_n,4(sp)
	beq	pccn
	inc	(sp)
pccn:	jsr	pc,putc
	mov	#'0,(sp)
	bit	#reg_psw_z,4(sp)
	beq	pccz
	inc	(sp)
pccz:	jsr	pc,putc
	mov	#'0,(sp)
	bit	#reg_psw_v,4(sp)
	beq	pccv
	inc	(sp)
pccv:	jsr	pc,putc
	mov	#'0,(sp)
	bit	#reg_psw_c,4(sp)
	beq	pccc
	inc	(sp)
pccc:	jsr	pc,putc
	tst	(sp)+
	rts	pc
print6:
	mov	r0,-(sp)
	mov	r1,-(sp)
	mov	6(sp),r0
	mov	#6,r1
p6g:	mov	r0,-(sp)
	bic	#~7,(sp)
	asr	r0
	asr	r0
	asr	r0
	bic	#0160000,r0
	sob	r1,p6g
	mov	#6,r1
p6p:	add	#'0,(sp)
	jsr	pc,putc
	tst	(sp)+
	sob	r1,p6p
	mov	(sp)+,r1
	mov	(sp)+,r0
	rts	pc
crlf:
	mov	#13.,-(sp)
	jsr	pc,putc
	mov	#10.,(sp)
	jsr	pc,putc
	tst	(sp)+
	rts	pc
puts:
	mov	r0,-(sp)
	mov	4(sp),r0
	clr	-(sp)
putsl:	movb	(r0)+,(sp)
	beq	putsx
	jsr	pc,putc
	br	putsl
putsx:	tst	(sp)+
	mov	(sp)+,r0
	rts	pc
putc:
	bit	#cons_ocsr_rdy,@#cons_ocsr
	beq	putc
	movb	2(sp),@#cons_obuf
	rts	pc
;. = (. + 777) & ~777;
nzvc_str:
	.asciz	"NZVC="